Method and apparatus to enhance processor power management
US7155621B2 · kind B2 · utility
15Cited by
24References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 26, 2001 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | Jun 10, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus to dynamically transition a processor between two performance states, high performance and low power. Predetermined core clock frequency and supply voltage levels of the processor define each performance state. Transitioning the supply voltage while the processor is in the active mode and transitioning the frequency while the processor is in the sleep mode significantly reduce the processor latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.