MOS transistor with recessed gate and method of fabricating the same
US7157770B2 · kind B2 · utility
8Cited by
10References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 1, 2004 |
| Grant date | Jan 2, 2007 |
| Priority date | — |
| Expiry date | Jul 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/016
Abstract
A MOS transistor with a recessed gate and a method of fabricating the same: The MOS transistor comprises a semiconductor substrate, and a trench isolation layer located in a predetermined region of the semiconductor substrate for defining an active region. The trench isolation layer has a negative slope on at least a lower sidewall thereof. A recessed gate is located in a predetermined region of the active region, and a bottom surface of the recessed gate is placed adjacent the negatively slopped sidewall of the trench isolation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.