Programmable asynchronous pipeline arrays
US7157934B2 · kind B2 · utility
74Cited by
7References
26Claims
0Family size
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Key dates
| Filing date | Aug 19, 2004 |
| Grant date | Jan 2, 2007 |
| Priority date | — |
| Expiry date | Oct 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
High-performance, highly pipelined asynchronous FPGAs employ a very fine-grain pipelined logic block and routing interconnect architecture. These FPGAs, which do not use a clock to sequence computations, automatically “self-pipeline” their logic without the designer needing to be explicitly aware of all pipelining details. The FPGAs include arrays of logic blocks or cells that include function units, conditional units and other elements, each of which is constructed using basic asynchronous pipeline stages, such as a weak condition half buffer and a precharge half buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.