Switched capacitor input circuit and method therefor
US7157956B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 3, 2004 |
| Grant date | Jan 2, 2007 |
| Priority date | — |
| Expiry date | Feb 9, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/005
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A switched capacitor input circuit (200) includes an input buffer (210), a switched capacitor sampler circuit (220), and an integrator (250). The input buffer (210) has an input terminal for receiving an input voltage, and an output terminal. The switched capacitor sampler circuit (220) has an input terminal coupled to the output terminal of the input buffer (210), and an output terminal. The switched capacitor sampler circuit (220) includes a capacitor (222) and stores a charge proportional a voltage at the output terminal of the input buffer (210) in the capacitor (222) during a sample period, and transfers the charge from the capacitor (222) to the output terminal thereof during a transfer period subsequent to the sample period in a plurality of charge portions corresponding to a like plurality of phases of the transfer period. The integrator (250) has an input terminal coupled to the output terminal of the switched capacitor sampler circuit, and an output terminal for providing an output voltage signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.