Ternary bit line signaling
US7158403B2 · kind B2 · utility
8Cited by
11References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 4, 2004 |
| Grant date | Jan 2, 2007 |
| Priority date | — |
| Expiry date | Mar 4, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is disclosed having a plurality of dual-bit addressable memory cells. In each memory cell, a first storage circuit for storing a first bit may be activated or de-activated depending upon the state of a second bit stored in a second storage circuit. The second bit may be considered to be a “don't care” bit, because depending upon the state of the second bit, the first bit may be irrelevant in that it cannot be read. Thus, each memory cell may effectively store three states: zero, one, and don't care.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.