Network packet buffer allocation optimization in memory bank systems
US7158438B2 · kind B2 · utility
2Cited by
4References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2005 |
| Grant date | Jan 2, 2007 |
| Priority date | — |
| Expiry date | Apr 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1042
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arrangement of buffer in a memory unit including a plurality of memory banks may store information in rows that span the memory banks. Moreover, a processor may be adapted to (i) establish a plurality of buffers to be associated with the memory unit, wherein the size of each buffer is less than the width of a memory bank, and (ii) arrange for a selected buffer to begin in a memory bank other than a memory bank in which a previously selected buffer begins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.