Timing control in data receivers and transmitters
US7158562B2 · kind B2 · utility
2Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2003 |
| Grant date | Jan 2, 2007 |
| Priority date | — |
| Expiry date | Mar 18, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03484
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A Gigabit transceiver (1) has a receiver (2) and a transmitter (3). There is an ADC (5) in the receiver (2) for each channel (A, B, C, D). The ADCs (5) oversample at a factor of 2. However the remainder of the digital circuitry and transmitter DACs (2) operate off half of the oversampling rate. In the receiver (2) fractionally spaced equalisers (FSES, 6) ensure that the optimum sampling phase is selected digitally. The invention avoids the need for a PLL in the receiver for each channel and associated interference and retiming problems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.