Charge pump phase locked loop
US7158600B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2002 |
| Grant date | Jan 2, 2007 |
| Priority date | — |
| Expiry date | Nov 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0895
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase lock loop circuit 60 has a phase frequency detector 62, a charge pump 64, an active filter 87 and a voltage-controlled oscillator 100. The phase detector generates UP and DN signals indicative of the relative frequency of FR, a reference signal, and FV, a signal controlled by the voltage-controlled oscillator. A charge pump using logic gates (buffer 66 and inverter 68) to produce a voltage drop over resistors 74 and 84 to generate a voltage at a node coupled to the input of transmission gate 76 according to the values of the UP and DN signals. When the transmission gate 76 is closed (low impedance) the charge pump may sink or source current to the inverting input of the operational amplifier 86 of the active filter 86. When the transmission gate is open (high impedance state) the inverting input is electrically isolated from the node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.