10 Gbit/sec transmit structure with programmable clock delays
US7158727B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2002 |
| Grant date | Jan 2, 2007 |
| Priority date | — |
| Expiry date | Aug 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J2203/0089
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The present invention provides a robust solution to the task of re-aligning data at the transmit end of a fiber optic or other high performance serial link, and also offers flexibility in the circuit board design approach. A high performance analog phase locked-loop circuit is used to simultaneously provide clock recovery for multiple bit streams. The power dissipation required to perform clock recovery is thereby reduced to a fraction of that required in conventional transmit systems. This analog phase locked loop produces plural phase output signals. An output multiplexer selects one phase for use in electrical to optical conversion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.