Method and apparatus for measuring switching noise in integrated circuits
US7159160B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2004 |
| Grant date | Jan 2, 2007 |
| Priority date | — |
| Expiry date | Apr 12, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3016
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A simultaneous switching noise (SSN) test circuit and method are provided for measuring effects of SSN. Prior to testing for SSN, a signal is applied to the victim signal input pad and the rise and fall time delays associated with the victim signal are measured at the victim signal output pad. Then, one or more aggressor signals are simultaneously applied to respective input pads of one or more respective aggressor signal paths. The rise and fall time delays of the victim signal transmitted by the output pad are then measured and compared to the previously measured rise and fall time delays to determine effects of SSN on the victim signal caused by the aggressor signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.