Iterative decoding with likelihood weighting
US7159168B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2003 |
| Grant date | Jan 2, 2007 |
| Priority date | — |
| Expiry date | Apr 7, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0071
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The invention relates to an error correcting decoder apparatus (100) and method. The decoder apparatus (100) comprises a likelihood estimator (101) which generates a sequence of bit value likelihood estimates, such as log likelihood ratios, for multi bit symbols of a data sequence. The decoder apparatus (100) further comprises a decoder element (103), such as a Maximum A Priori (MAP) or appropriate Soft Output Viterbi decoder. The decoder element (103) generates a decoded data sequence in response to the bit value likelihood estimates. The decoder apparatus (100) also comprises a weighted processor (105) which generates a weighted compensation data sequence from the decoded data sequence. The weighted compensation data is used to modify the sequence of bit value likelihood estimates. The decoding is subsequently repeated using the improved bit value likelihood estimates whereby improved decoding performance is achieved. The invention may be applied to a two decoder element decoding apparatus (200) and may specifically be applied to turbo decoders.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.