Method of bumping die pads for wafer testing
US7160797B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 3, 2005 |
| Grant date | Jan 9, 2007 |
| Priority date | — |
| Expiry date | May 3, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of processing a semiconductor wafer including a plurality of semiconductor dies is provided. The method includes providing a semiconductor wafer including a plurality of semiconductor dies, at least a portion of the semiconductor dies including contact pads for testing the respective semiconductor die. The method also includes positioning conductive bumps on the contact pads prior to completing wafer testing of the semiconductor wafer and prior to the singulation of the plurality of semiconductor dies from the semiconductor wafer. At least a portion of the conductive bumps are configured to be electrical paths during wafer testing of the semiconductor wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.