Adaptive bus voltage positioning for two-stage voltage regulators
US7161335B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2004 |
| Grant date | Jan 9, 2007 |
| Priority date | — |
| Expiry date | Sep 22, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Alteration of voltage input to a voltage regulator output stage from a Vbus regulator stage in a two-stage voltage regulator provides optimal Vbus voltage placement for a wide range of current loads to increase voltage regulator efficiency and is particularly suited to CPUs having power-saving sleep modes of operation. An optimal voltage is selected or developed in response to information concerning operational mode or current consumption of the powered device. As a perfecting feature of one embodiment of the invention in which a discrete Vbus voltage is selected based on operational mode, the selected voltage is adjusted to further optimize the matching of the Vbus voltage placement to the load and provides a continuous range of voltages. In a second embodiment the entire Vbus positioning function is performed in response to current load information. A feed-forward arrangement is provided to avoid transient spikes as the Vbus voltage placement is altered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.