Multi-stage analog to digital converter architecture
US7161521B2 · kind B2 · utility
2Cited by
5References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2005 |
| Grant date | Jan 9, 2007 |
| Priority date | — |
| Expiry date | Jul 27, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
According to an aspect of the present invention, different reference voltage levels are used for different stages of a multi-stage analog to digital converter (ADC). In one embodiment, the amplification and unity gain bandwidth (UGB) requirements in the first stage is reduced as a result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.