TFT display controller
US7161571B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2004 |
| Grant date | Jan 9, 2007 |
| Priority date | — |
| Expiry date | Jul 15, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/18
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A programmable controller having three well-known components used in display controls but put under the control of a programmable ‘sub-field ’ timing generator is disclosed. The three well-known components include a Phase Lock Loop (PLL) unit, a Pixel Pipe Line (PPL) unit and an embedded frame buffer. Even though these are well known and understood components, each one is implemented to support the field and sub-field concepts of field sequential color (FSC) as well as non-FSC TFT display devices. The programmable controller also includes some new components that are unique to FSC displays. These new components include a color light sequencer to control the LED controls (or whatever color light source used) and programmable Source and Gate driver controls to accommodate the extremely wide diversification between different display panels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.