System for arraying surface mount grid array contact pads to optimize trace escape routing for a printed circuit board
US7161812B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 20, 2003 |
| Grant date | Jan 9, 2007 |
| Priority date | — |
| Expiry date | Dec 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10734
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A surface mount grid array implemented on a PCB (printed circuit board) optimized for trace escape routing for the PCB. The surface mount grid array includes a plurality of connection blocks, with each connection block including an array of pins and an array of vias, wherein the pins and vias are configured to communicatively connect an integrated circuit device to a plurality of traces of the PCB. The connection blocks are disposed in a tiled arrangement, wherein the connection blocks implement a plurality of trace escape channels along connection block boundaries. The trace escape channels are configured for routing traces from inner pins of the surface mount grid array to a periphery of the surface mount grid array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.