Jitter and skew suppressing delay control apparatus
US7161854B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 27, 2005 |
| Grant date | Jan 9, 2007 |
| Priority date | — |
| Expiry date | Jun 27, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0805
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay control apparatus includes first and second delay elements each configured to receive and delay a strobe signal and clock by a prescribed delay value. A prescribed number of flip-flops is provided to input data upon receiving the strobe signal output from the second delay element. The second delay element delays and outputs the strobe signal by the prescribed delay value to the flip-flops when the selection device selects the strobe signal. A phase comparator compares clocks output from the first and second delay elements. A delay control device changes the prescribed delay value of the second delay element in accordance with the comparison result of the phase comparator when the selection device selects the clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.