Semiconductor memory device
US7161867B2 · kind B2 · utility
9Cited by
6References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 1, 2006 |
| Grant date | Jan 9, 2007 |
| Priority date | — |
| Expiry date | Feb 1, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory device, sub-macros are connected sequentially onto an interface unit in which each sub-macro includes a data control unit connected to the interface unit through a global data line, a first memory block and a second memory block. The first memory block is connected to one side of the data control unit through a first local data line, and the second memory block is connected to the other side of the data control unit through a second local data line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.