Add/drop multiplexor with aggregate serializer/deserializers
US7161965B2 · kind B2 · utility
24Cited by
9References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 29, 2002 |
| Grant date | Jan 9, 2007 |
| Priority date | — |
| Expiry date | Dec 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/08
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A telecommunications node architecture is disclosed that facilitates the loop-back of a signal in an add/drop multiplexor (e.g., a SONET/SDH node, a dense wavelength division multiplexed node, etc.) that uses automatic protection switching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.