Correlating high-speed serial interface data and FIFO status signals in programmable logic devices
US7162553B1 · kind B1 · utility
10Cited by
3References
32Claims
0Family size
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Key dates
| Filing date | Oct 1, 2004 |
| Grant date | Jan 9, 2007 |
| Priority date | — |
| Expiry date | Jan 26, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G1/0094
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Status signals that are generated by one or more FIFO buffers in a high-speed serial interface (“HSSI”) may be combined with transmitted data samples in order to correlate the status signals to the respective data samples. The combined data and status signals may be transmitted either to the subsequent stages of the HSSI datapath or directly to the PLD via a dedicated path with less latency. The combined data and status signals can be used to determine whether a data sample corresponds to a valid data sample or an idle sequence, thereby allowing a user to control the flow of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.