Data processor with changeable architecture
US7162617B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2003 |
| Grant date | Jan 9, 2007 |
| Priority date | — |
| Expiry date | Jun 24, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A program counter having an independent context for each virtual processor is provided, and a non-native instruction fetched from a main memory based on address information generated by the program counter is classified by property by an instruction classifying unit. Then an instruction merge information memory is read out utilizing address information prescribed for each classified group as reference address, and native execution control information is merged and executed. Selection and switching of the virtual processor is performed through selectively switching the instruction classifying unit and an active portion of the instruction merge information memory, and the switching timing is appropriately adjusted by synchronizing with a switching enabling signal output from the instruction merge information memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.