System and method for testing memory during boot operation idle periods
US7162625B2 · kind B2 · utility
6Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2003 |
| Grant date | Jan 9, 2007 |
| Priority date | — |
| Expiry date | Jul 12, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4403
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses an information handling system that reduces POST time in a boot operation. The information handling system includes a processor, a memory and a BIOS unit. The BIOS also includes memory test pointer and a test block size indicator. During the POST routine, the BIOS tests at least one test block during at least one idle period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.