Method for manufacturing semiconductor integrated circuit structures
US7163898B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2003 |
| Grant date | Jan 16, 2007 |
| Priority date | — |
| Expiry date | Jul 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing circuit structures integrated in a semiconductor substrate that includes regions, in particular isolation regions, includes the steps of:—depositing a conductive layer to be patterned onto the semiconductor substrate;—forming a first mask of a first material on the conductive layer;—forming a second mask made of a second material that is different from the first and provided with first openings of a first size having spacers formed on their sidewalls to uncover portions of the first mask having a second width which is smaller than the first;—partly etching away the conductive layer through the first and second masks such to leave grooves of the second width;—removing the second mask and the spacers; and—etching the grooves through the first mask to uncover the regions provided in the substrate and form conductive lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.