Field programmable gate array logic unit and its cluster
US7164290B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 26, 2004 |
| Grant date | Jan 16, 2007 |
| Priority date | — |
| Expiry date | Jan 21, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The embodiments of the present invention relate to the general area of the Field Programmable Gate Arrays, and, in particular to the architecture and the structure of the building blocks of the Field Programmable Gate Arrays. The proposed logic units, as separate units or cluster of units, which are mainly comprised of look-up tables, multiplexers, and a latch, implement functions such as addition, subtraction, multiplication, and can perform as shift registers, finite state machines, multiplexers, accumulators, counters, multi-level random logic, and look-up tables, among other functions. Having two outputs, the embodiments of the logic unit can operate in split-mode and perform two separate logic and/or arithmetic functions at the same time. Clusters of the proposed logic units, which utilize local interconnections instead of traditional routing channels, add to efficiency, speed, and reduce required real estate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.