Runt-pulse-eliminating multiplexer circuit
US7164296B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2004 |
| Grant date | Jan 16, 2007 |
| Priority date | — |
| Expiry date | Mar 26, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiplexer circuit for selecting one of first and second input signals based on a first input select signal includes a multiplexer, a control circuit and an enable buffer. The multiplexer selects one of the first and second input signals based on a second input select signal generated by the control circuit and provides a second output signal. The control circuit receives the second output signal and the first input select signal to generate the second input select signal and an enable signal where the signals have transitions synchronized to the transitions of the second output signal. The enable buffer operates to allow or disallow the second output signal to be passed as the output signal of the multiplexer circuit in response to the enable signal. The multiplexer circuit operates to eliminate runt pulse generation during the switching over of the input signals to provide an error-free output data stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.