Display controller and display device provided therewith
US7164415B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2002 |
| Grant date | Jan 16, 2007 |
| Priority date | — |
| Expiry date | Sep 10, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/18
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention can realize better display of a dynamic image, and in addition, can make storage capacity of a memory smaller. A data conversion circuit 112 compares display data 102 of an n-th frame from the outside and display data 116 of the (n−1)-th frame stored in the memory 104, to generate a driving data signal 117 to deliver to a driver. Each time when a memory control circuit 103 reads display data q0, q5, q10, q15 corresponding to 20 pixels out of the display data 116 of the (n−1)-th frame, the memory control circuit 103 compresses display data d0–d19 of 20 pixels out of the display data 102 of the n-th frame from the outside to generated d0, d5, d10, d15, and stores the generated data into the same area where the display data q0, q5, q10, q15 of the display data of the (n−1)-th frame have been stored.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.