Patent · US Expired

Phase-locked loop for synchronization with a subcarrier contained in an intelligence signal

US7164735B2 · kind B2 · utility

3Cited by
7References
28Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 11, 2002
Grant dateJan 16, 2007
Priority date
Expiry dateDec 13, 2023

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03J7/04
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

A phase-locked loop locks relatively quickly to a pilot tone of the stereo-multiplex signal when a new transmitter is tuned in. The stereo-multiplex signal may be multiplied in a multiplier by the quadrature component of the pilot tone generated by a digital oscillator. The result is a control signal that is provided to a low-pass filter, and the low-pass filtered control signal is provided as a control signal to an oscillator which may include a table of length N and a counter for addressing the table entries. The zero phase angle φ0 may be set by a counter offset n0 by incrementing or decrementing the counter. A table may be utilized having a virtual length N+ which is larger than the length N of the real table. To access the real table, however, the corresponding MSBs of the actual count n(k) are used which match the address space of the real table of length N.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.