Method, system, and apparatus for bit error capture and analysis for serial interfaces
US7165195B2 · kind B2 · utility
2Cited by
5References
26Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 15, 2003 |
| Grant date | Jan 16, 2007 |
| Priority date | — |
| Expiry date | May 27, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/277
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method to facilitate validation and/or test of serial interfaces by analyzing error event types based at least in part on a code-stamp, compare engine logic and a memory for error capture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.