Tap time division multiplexing
US7165199B2 · kind B2 · utility
8Cited by
9References
26Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 17, 2004 |
| Grant date | Jan 16, 2007 |
| Priority date | — |
| Expiry date | Jun 29, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318536
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test data, wherein the test data is clocked in a plurality of time slots, with test data for different ones of the plurality of portions being allocated to different time slots.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.