System and method for characterizing a signal path using a sub-chip sampler
US7165200B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2005 |
| Grant date | Jan 16, 2007 |
| Priority date | — |
| Expiry date | May 5, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/11
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method are disclosed for characterizing a signal path. The system includes a system clock configured to produce a system clock signal at a sample frequency. A frequency divider is configured to divide the sample frequency of the system clock signal by a factor of N to produce a chip clock signal at a chip frequency. The system further includes a pseudo-noise (PN) sequence generator configured to produce a PN sequence at the chip frequency and couple the PN sequence to the signal path while the signal path is carrying an operational signal. A sub-chip sampler is configured to correlate the PN sequence and a reflected PN sequence which has been reflected within the signal path to form a correlated signal and to sample the correlated signal at the sample frequency of the system clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.