Method and apparatus for encoding and decoding data
US7165205B2 · kind B2 · utility
15Cited by
1References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 23, 2004 |
| Grant date | Jan 16, 2007 |
| Priority date | — |
| Expiry date | Apr 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1185
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for interlacing columns of different weights is proposed for a parity-check matrix H that results in good performing LDPC codes shortened or unshortened. Matrix H comprises a section H1 and a section H2, and wherein H1 has a plurality of different column weights and comprises a plurality of sub-matrices where columns of at least one weight are substantially interlaced between the sub-matrices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.