SRAM-compatible memory for correcting invalid output data using parity and method of driving the same
US7165206B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2003 |
| Grant date | Jan 16, 2007 |
| Priority date | — |
| Expiry date | Dec 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4062
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is an SRAM-compatible memory for correcting invalid output data using parity and a method of driving the same. In the SRAM-compatible memory, input data and a parity value obtained from the input data are written in data banks and parity bank, respectively. When invalid data is output from a specific memory bank due to the performance of a refresh operation or other factors, the invalid data are corrected by a data corrector using the parity value written in the parity bank, thus generating output data having the same logic value as the input data. The SRAM-compatible memory prevents a reduction in operation speed due to an internal operation, such as a refresh operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.