Semiconductor memory device having a gate electrode and a method of manufacturing thereof
US7166889B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2003 |
| Grant date | Jan 23, 2007 |
| Priority date | — |
| Expiry date | Mar 26, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A first aspect of the present invention is providing a non-volatile semiconductor memory device, comprising: a memory cell having a tunnel oxide layer formed on a semiconductor substrate, a floating gate formed on the tunnel oxide layer, a control gate to which voltage is supplied, a source diffusion layer and a drain diffusion layer, the source and drain diffusion layers formed in the semiconductor substrate adjacent to the tunnel oxide layer; a contact layer connected to the drain diffusion layer; and a layer formed above the memory cell, the layer comprising at least one of: 1) a silicon oxide layer to which nitrogen are doped, 2) a silicon oxide layer to which aluminum are doped, 3) an aluminum oxide layer, 4) a silicon oxide layer to which titanium are doped, 5) a silicon oxide layer to which two of nitrogen, aluminum, and titanium are doped, 6) a silicon oxide layer to which nitrogen, aluminum, and titanium are doped, 7) a titanium oxide layer, 8) a titanium and aluminum oxide layer, 9) a simple metal layer comprising one of Ti, Ni, Co, Zr, Cu, Pt, V, Mg, U, Nd, La, and Sc, 10) an alloy layer comprising at least two of Ti, Ni, Co, Zr, Cu, Pt, V, Mg, U, Nd, La, and Sc, and the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.