Flip chip FET device
US7166898B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 12, 2005 |
| Grant date | Jan 23, 2007 |
| Priority date | — |
| Expiry date | Aug 12, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In accordance with one embodiment of the invention, a semiconductor device includes conductive pad areas, and each conductive pad area is electrically connected to a plurality of metal traces which are in turn each connected to diffusions. A conductive contact element such as a solder bump or via can be attached to each conductive pad area such that the contact elements are arranged in a repeating pattern having a first pitch. The semiconductor device can also include translation traces, and each translation trace can be electrically connected to two or more of the conductive contact elements. Each translation trace can have a interconnect element attached thereto. The interconnect elements can be arranged in a repeating pattern having a second pitch substantially greater than the first pitch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.