High performance analog charge pumped phase locked loop (PLL) architecture with process and temperature compensation in closed loop bandwidth
US7167056B2 · kind B2 · utility
5Cited by
5References
14Claims
0Family size
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Key dates
| Filing date | Sep 30, 2004 |
| Grant date | Jan 23, 2007 |
| Priority date | — |
| Expiry date | Sep 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/04
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention achieves technical advantages as a high performance analog charge pumped phase locked loop (PLL)(10) with process and temperature compensation in closed loop bandwidth. The PLL reduces the variation in bandwidth and stability by making the product KVCO*ICP independent of process and temperature variation. The PLL achieves a higher performance than existing PLL architectures, achieving a high dynamic range up to at least 110 dB, such that a PWM class-D amplifier is realizable with this PLL. The PLL has a constant bandwidth and damping factor while using an analog charge pump (16).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.