Delta-sigma modulators with double sampling input networks and systems using the same
US7167119B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2005 |
| Grant date | Jan 23, 2007 |
| Priority date | — |
| Expiry date | Dec 20, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/452
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of sampling an input signal in a delta-sigma modulator having at least an integrator stage and a feedback digital-to-analog converter (DAC) stage includes sampling an input signal at a sampling rate by alternately utilizing the two sampling capacitors during two sampling cycles such that the two sampling capacitors are each being utilized at half the rate of the sampling rate. Samples from the two sampling capacitors are summed at the sampling rate at an intermediate node with a feedback samples provided by the feedback DAC stage at the sampling rate to generate output samples which are output from integrator stage at the sampling rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.