Processing of quinary data
US7167514B2 · kind B2 · utility
5Cited by
10References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2002 |
| Grant date | Jan 23, 2007 |
| Priority date | — |
| Expiry date | Aug 17, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0225
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A FIR filter in a Gigabit transceiver in which data words are represented in three bits: SIGN representing word sign, SHIFT representing requirement for a shift operation, and ZERO indicating whether the word is zero. An AND gate ANDs an input coefficient and the ZERO bit, an XOR gate XORs the SIGN bit and the output of the AND gate, and a multiplier left-shifts the coefficient using the SHIFT bit and the output of the XOR gate. The circuit has a very low gate count.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.