Wireless communications transceiver: transmitter using a harmonic rejection mixer and an RF output offset phase-locked loop in a two-step up-conversion architecture and receiver using direct conversion architecture
US7167686B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2003 |
| Grant date | Jan 23, 2007 |
| Priority date | — |
| Expiry date | Dec 1, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D2200/0086
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A wireless transceiver includes a transmitter having a harmonic rejection mixer and an RF output phase-locked loop in a two step up-conversion architecture, and a direct conversion receiver. The transmitter includes a local oscillator for producing a signal at a multiple of an intermediate frequency, a quadrature modulator harmonic rejection mixer responsive to the signal at the multiple of the intermediate frequency for modulating in-phase and quadrature-phase base-band signals to produce an intermediate frequency signal, a filter responsive to the intermediate frequency signal for producing a filtered intermediate frequency signal, and an RF output offset phase-locked loop responsive to the filtered intermediate frequency signal and the signal at the multiple of the intermediate frequency for producing an RF transmission signal. The harmonic rejection mixer reduces filtering requirements to facilitate a high level of circuit integration. The local oscillator may use a integer or fractional-N phase-locked loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.