Filter with multipliers operating in ones complement arithmetic
US7167883B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2002 |
| Grant date | Jan 23, 2007 |
| Priority date | — |
| Expiry date | Apr 8, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03617
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A finite impulse response filter, including a plurality of taps arranged to receive and process a sequence of input data samples so as to generate a filter output. Each tap consists of a multiplier operating in one's complement arithmetic, the multiplier being coupled to multiply a respective input sample from the sequence by a respective equalization coefficient, and an adder, which sums an output from the multiplier. The taps are arranged in sequence so that the input sample to each of the taps, except to a first tap in the sequence, is delayed relative to a preceding tap in the sequence. The filter also includes an adjustment-accumulator coupled to receive the filter output and responsive thereto to generate an adjustment that is adapted to correct the filter output to a twos complement result, and an adjustment-adder which sums the adjustment and the filter output to generate a final output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.