Memory module and memory-assist module
US7167967B2 · kind B2 · utility
30Cited by
6References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2003 |
| Grant date | Jan 23, 2007 |
| Priority date | — |
| Expiry date | Jul 18, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer body outputting a predetermined number of address signals A0 to A11 and a plurality of select signals CSO and CSI, generates a memory select signal CS and an additional address signal A12 added to the signals A0 to A11 according to the inputted signals CSO and CSI, and provides the signal CS, signal A12, and signals A0 to AI1 to a 256-megabit SDRAM (memory), so that the computer body can access the corresponding data. The computer body can access the data corresponding to the generated additional address signal A12 and predetermined number of the address signals A0 to A11.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.