Circuit and method for testing embedded phase-locked loop circuit
US7168020B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2003 |
| Grant date | Jan 23, 2007 |
| Priority date | — |
| Expiry date | Oct 11, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/1403
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and a device for testing an embedded phase-locked loop (PLL) circuit are disclosed. A first clock signal of a first frequency is provided to an embedded phase-locked loop (PLL) circuit to be tested by a tester, so as to generate a PLL clock signal by the embedded PLL circuit in response to the first clock signal of the first frequency. The PLL clock signal is inputted to a test circuit along with a second clock signal of a second frequency. Then, the PLL clock signal is sampled with the second clock signal of the second frequency to generate a first sampled signal. The second frequency has a first correlation with the first frequency. Whether the embedded PLL circuit is in a normal operation condition is determined according to the first sampled signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.