Aggregate bandwidth through management using insertion of reset instructions for cache-to-cache data transfer
US7168070B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2004 |
| Grant date | Jan 23, 2007 |
| Priority date | — |
| Expiry date | Mar 5, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/383
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for reducing or avoiding store misses with a data cache block zero (DCBZ) instruction in cooperation with the underlying hardware load stream prefetching support for helping to increase effective aggregate bandwith. The method identifies and classifies unique streams in a loop based on dependency and reuse analysis, and performs loop transformations, such as node splitting, loop distribution or stream unrolling to get the proper number of streams. Static prediction and run-time profile information are used to guide loop and stream selection. Compile-time loop cost analysis and run-time check code and versioning are used to determine the number of cache lines ahead of each reference for data cache line zeroing and to tolerate required data alignment relative to data cache lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.