Method for making a system for selecting one wire from a plurality of wires
US7169696B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2004 |
| Grant date | Jan 30, 2007 |
| Priority date | — |
| Expiry date | Aug 12, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A system and method for selecting nanometer-scaled devices. The method includes a plurality of semiconductor wires. Two adjacent semiconductor wires of the plurality of semiconductor wires are associated with a separation smaller than or equal to 100 nm. Additionally, the system includes a plurality of address lines. Each of the plurality of address lines includes a gate region and an inactive region and intersects the plurality of semiconductor wires at a plurality of intersections. The plurality of intersections includes a first intersection and second intersection. The first intersection is associated with the gate region, and the second intersection is associated with the inactive region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.