Output buffer with selectable slew rate
US7170324B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2004 |
| Grant date | Jan 30, 2007 |
| Priority date | — |
| Expiry date | Jul 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/163
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer design for an integrated circuit that has adjustable slew rate control, yet requires significantly less space to fabricate than does a conventional buffer with slew rate control. A new slew rate control circuit design is added to a Complementary Metal Oxide Semiconductor CMOS buffer to implement slew rate control in the buffer (e.g., selection between a high slew rate and a low slew rate). The new slew rate control circuit requires significantly less space to fabricate, and when applied to each buffer in an given integrated circuit, e.g., input/output buffers that may be placed along the periphery of the integrated circuit, the savings can be extraordinary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.