Two-bit offset cancelling A/D converter with improved common mode rejection and threshold sensitivity
US7170437B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2005 |
| Grant date | Jan 30, 2007 |
| Priority date | — |
| Expiry date | Nov 10, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/36
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A two-bit offset canceling A/D converter with improved common mode rejection and threshold sensitivity for use in GPS receivers. A device in accordance with the present invention comprises a level shifter, the level shifter receiving a positive signal and a negative signal, the level shifter shifting the positive signal and the negative signal such that a difference between the positive signal and the negative signal is larger than a threshold value, and a comparator, coupled to the level shifter, the comparator providing as outputs of the comparators a sign bit and two magnitude bits wherein the comparator comprises a plurality of switched capacitor amplifiers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.