High performance and reduced area architecture for a fully parallel search of a TCAM cell
US7170769B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2005 |
| Grant date | Jan 30, 2007 |
| Priority date | — |
| Expiry date | Oct 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique to enhance performance and reduce silicon area for a TCAM system which includes a plurality of CAM blocks that are organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of TCAM cells and associated read/write bit lines connecting the group of CAM cells to search bit lines. Each TCAM cell in the TCAM architecture includes a pair of memory elements that is connected to a pair of associated compare circuits such that the interconnections between the memory elements and the compare circuits are substantially vertical in active MOS layers and substantially horizontal in the metal layers to facilitate sharing of adjacent cells thereby providing reduced silicon area and a short aspect ratio.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.