Access of two synchronous busses with asynchronous clocks to a synchronous single port ram
US7170817B2 · kind B2 · utility
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4References
14Claims
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Key dates
| Filing date | Jun 16, 2004 |
| Grant date | Jan 30, 2007 |
| Priority date | — |
| Expiry date | Jul 21, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit are provided for controlling access of two synchronous busses with asynchronous clocks to a synchronous single port Random Access Memory (RAM). In one preferred method, the clock of bus A is switched off via a control flip-flop and then the clock of bus B is switched on, allowing the control and data signals to pass through simple multiplexers. Bus B becomes the owner of the RAM. Later, the clock of bus B is switched off via the control flip-flop and then clock of bus A is switched on, such that bus A becomes owner of the bus. This allows any relative speed between the bus clocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.