Clock recovery method by phase selection
US7170963B2 · kind B2 · utility
1Cited by
8References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 15, 2003 |
| Grant date | Jan 30, 2007 |
| Priority date | — |
| Expiry date | Feb 26, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention demonstrates a method and circuit where a plurality of phase clocks from a “frequency lock only” PLL are used to sample an input clock CLKIN. This results in a series of signals from which the phase clock most in synchronization with CLKIN can be determined and presented to the output CLKOUT. If used for data sampling, a phase clock that lags the phase clock most in synchronization may be selected to appear at CLKOUT. This guarantees that sampled data are static during sampling. This system is less complex and consumes minimal power over systems using variable delay circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.