Logic verification in large systems
US7171347B2 · kind B2 · utility
7Cited by
7References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 2, 1999 |
| Grant date | Jan 30, 2007 |
| Priority date | — |
| Expiry date | Jan 3, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of preparing a circuit model for simulation comprises decomposing the circuit model having a number of latches into a plurality of extended latch boundary components and partitioning the plurality of extended latch boundary components. Decomposing and partitioning the circuit model may include decomposing hierarchical cells of the circuit model, and using a constructive bin-packing heuristic to partition the plurality of extended latch boundary components. The partitioned circuit model is compiled, and simulated on a uni-processor, a multi-processor, or a distributed processing computer system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.