Processing and verifying retimed sequential elements in a circuit design
US7171634B2 · kind B2 · utility
10Cited by
0References
33Claims
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Assignee
Inventors
Key dates
| Filing date | Jun 28, 2004 |
| Grant date | Jan 30, 2007 |
| Priority date | — |
| Expiry date | Jan 7, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are a method, system, and program for processing and verifying circuit designs. A circuit design specification written in a hardware definition language is received and zero delay black box code is added to the circuit design specification to position the zero delay black boxes at sequential elements. A synthesis of the circuit design specification is performed to generate a retimed implementation of the circuit design specification. The black boxes are processed in the retimed implementation to verify the synthesis of the circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.